Course Overview

The “Elaboration System Architectures” (ASE) course starts in the first semester of the Computer Science master course first year. It comprehends 9 CFU, split in 51 hours in lessons, 18 hours in exercises and 18 hours in practical laboratories, for a total of 87 hours. Student's estimated effort is of 2h per hour of lesson; 1h per hour of exercise and 1h per hour of practical laboratory. As 1 CFU = 24h, whose 12h are for lesson, 6h for exercises and 6 for practical laboratory, from the course 9 CFU derives a load for the student of 9 CFU x 24h = 216h. These hours of work are so divided: 12 x 9 = 108h of lesson, 54h of exercises and 54h of practical laboratory. The professor will have to distribute, according to this load: 108/3 = 36h of lesson; 54/2 = 27h of exercises; 54/2 = 27h of practical laboratory; for a total of 90 hours in 13 weeks, with 7h per week.

Prerequisites

The course widely refers to the arguments already treated by the courses of “Fundamentals of Computer Science I and II”, “Logical Networks” and “Computers Architectures I” of the bachelor course of studies.

Educational Goals

The course supplies the student with designing methodologies basics, needed for modern digital systems realisation (microprocessor systems, sensors and I/O devices). The student will acquire methods and techniques for the components design of dedicated elaboration systems (embedded systems) and general purpose elaboration systems. Moreover, he/she will acquire skills on the usage of hardware design tools and languages, needed by the entire development cycle of a medium complexity system, including the synthesis on FPGA and functional tests.

Course Organisation

The course comprehends face-to-face lessons and seminars on specific arguments for an in-depth analysis. Exercises and practical laboratory are hold in classroom. Students attending the course are split in groups (from 3 to 4 students each), which will realise concrete projects of digital systems make with the help of professional CAD tools. The course, mandatory for the master course computer science students, is strongly oriented to the digital design and attendance is required.

Final Examination

Exams happen monthly, excluding March. Students who are repeating the year can hold the examination following the program of the year in which they attended the course, or, under request, following the program of the current year after having agreed upon the lessons they will have to follow to integrate. The examinations consists of:

• An oral examination discussing all the topics treated during the course, with possible written exercises.
• A description of the papers developed during the exercises and of the group assigned project. All the papers have to be well documented and well written, according a given template.

Lessons organisation according to the course program

1. Source introduction. Level organisation of a digital system; general purpose, special purpose and embedded systems.
2. Informations and signals; positive and negative logic representation; 0-active and 1-active signals.
3. Digital systems design: technological and methodological aspects, support environments; digital system development, design flow and verification.
4. Sequential and combinational Logical networks; combinational multi-output networks; realisation of boolean functions through digital circuits; delays analysis and evaluation, signals deformations, power consumption.
5. Boolean functions minimisation with canonical forms and more; single and multi output combinational networks minimisation with exact methods (McCluskey) and heuristics, with the utilisation of automatic tools like Berkeley SIS.
6. Multi level minimisation of combinational networks; representation methods; algebraic model; algebraic and boolean transformations.
7. Synchronous and asynchronous, impulsive and level sequential machines; Huffmann and Muller models; sequential networks systems (open and closed chain sequential networks, pipeline architectures).
8. Synchronous sequential machines design.
9. Elements of asynchronous machine design working according to Huffmann and Muller models.
10. Handshaking types; C-Muller synchronisation network.
11. Programmable devices: PAL, PLA, FPGA and ASIC.
12. Develop process of digital systems design, synthesis and technological mapping.
13. Digital systems; functions and structural models of systems; micro operations and their description; system logic components; system operations; complex digital system architecture; Operative Part and Control Part model (PO/PC).
14. Wired-up control and micro controlled PC systems, micro languages and their classification.
15. HDL languages for hardware design: VHDL, Verilog and SystemC.
16. VHDL in-depth analysis; basic examples of VHDL devices description.
17. Arithmetic circuits design: adders and subtracters (ripple carry; carry save; carry look ahead) with VHDL description and simulation.
18. Arithmetic circuits design: multipliers (rows, columns and diagonals; MAC cells; Robertson and Booth) and divisors (sequential and with no restoring) with VHDL description and simulation.
19. System Data Path and its principal components: bus and interconnection networks; registers; Multiplexer and Demultiplexer; Decoder; Shifter; ALU; memories (ROM, PROM, E2PROM, static and dynamic RAM, Flash, etc..).
20. Synchronous and asynchronous bus.
21. Pipelined systems architectures.
22. General model of I/O devices architecture used in digital systems.
23. Transmission I/O devices project examples: parallel transmission, asynchronous serial transmission (UART) and synchronous serial transmission (USART).
24. Signals encoding and transmission: bit cell concept; tranmission channels; line encoding; Non Return to Zero (NRZ) encoding; Non Return to Zero Inverted encoding; Return to Zero encoding; Manchester encoding; Miller encoding; differential Manchester encoding; modified Manchester encoding; serial and parallel transmission; signal modulation.
25. Memory devices.

Exercises

1. Single and multi output combinational networks synthesis with SIS design tool.
2. Synchronous and asynchronous sequential networks synthesis.
3. Function and characteristics of IDE digital design environments.
4. Design process of a system described in VHDL.
5. VHDL digital design methodology.
6. Logical networks optimisation and technological mapping.
7. I/O device development (UART/PIO).
8. Digilent Nexys 2 board architectural description.
9. Digilent Nexys 2 board devices description (switch, buttons, seven segments display, serial port, usb, etc)

Practical Laboratory

(during the practical laboratory hours, the student will synthesise circuits proposed during the course).

1. SIS tool installation and utilisation for the logical networks design.
2. Combinational networks synthesis exercises with SIS tool and delays analysis.
3. Sequential networks synthesis exercises with SIS tool and delays analysis.
4. Xilinx ISE environment description for FPGA synthesis and design of devices.
5. VHDL description of basic combinational and sequential circuits. Simulation and synthesis on FPGA.
6. Datapath basic components (mux, demux, decoder, etc...) VHDL description. Simulation and synthesis on FPGA.
7. Adders and subtracters description. Simulation and synthesis on FPGA.
8. Multipliers and divisors description. Simulation and synthesis on FPGA.
9. Clock generators. Simulation and synthesis on FPGA.